1. Field of the Invention
The present invention relates to a semiconductor element in which a plurality of circuits such as, for example, an analog circuit and a digital circuit are mounted on a semiconductor substrate, and a semiconductor device and a mounting board including the semiconductor element, more particularly to a semiconductor element, a semiconductor device and a mounting board which are preferably used in the case where while a digital circuit uses a large-amplitude signal, an analog circuit uses a small signal of a few μV to a few mV.
2. Description of the Related Art
With an improvement in frequency characteristics of a CMOS (Complementary Metal Oxide Semiconductor) process in recent years, an analog circuit can be formed together with a digital circuit on one chip by the CMOS process. However, in the case where the analog circuit and the digital circuit are formed on one chip, compared to the case where the analog circuit and the digital circuit are separately formed on different chips, the digital circuit is positioned closer to the analog circuit, so in particular, in the case where while the digital circuit uses a large-amplitude signal, the analog circuit uses a small signal of a few μV to a few mV, noises generated in the digital circuit may exert an influence on the analog circuit. Therefore, typically, the analog circuit is arranged as far from the digital circuit which may be a noise source as possible in a chip.
FIG. 30 shows a plan view of a typical semiconductor element 100 in which an analog circuit 110 and a digital circuit 120 are mounted on a p-type semiconductor substrate 140. In FIG. 30, an interlayer insulating film 141 and a passivation layer 142 (which will be described later) of the semiconductor element 100 are not shown. FIG. 31 shows a simplified sectional view (that is, some parts are not shown) taken along a line A-A viewed from an arrow direction, and a parasitic capacity C101 formed between an n-type source region 111 or an n-type drain region 112 and the p-type semiconductor substrate 140. FIG. 32A shows a sectional view taken along a line B-B viewed from an arrow direction, and FIG. 32B shows a parasitic resistance R101 formed between a via 131 and a p-type semiconductor region 133 in a sectional view of FIG. 32A.
It is obvious from FIG. 30 that the analog circuit 110 is arranged in a corner of the chip in order to be arranged away from the digital circuit 120 which may be a noise source. For example, as simply shown in FIG. 31, the analog circuit 110 is electrically connected to the p-type semiconductor substrate 140 through the n-type source region 111 or the n-type drain region 112 of a transistor included in the analog circuit 110 and the parasitic capacity C101. Therefore, at a certain frequency or higher, the analog circuit 110 is coupled to the p-type semiconductor substrate 140 with low impedance, and the analog circuit 100 is susceptible to the potential of the p-type semiconductor substrate 140. In addition, the interlayer insulating film 141 and the passivation layer 142 formed by laminating a SiO2 layer 142A and a polyimide layer 142B in this order, are laminated on the p-type semiconductor substrate 140.
As shown in FIG. 33, the potential of the p-type semiconductor substrate 140 directly below the analog circuit 110 is susceptible, because noises generated in the digital circuit 120 propagate through the p-type semiconductor substrate 140 as a path path1. Therefore, in some cases, it is necessary to reduce noises (substrate noises) propagating through the path path1.
Therefore, for example, as shown in FIG. 34, it can be considered that a deep n-type well layer 143 and an n-type well layer 144 which separate the analog circuit 110 from the other portion of the p-type semiconductor substrate 140 are arranged (refer to Japanese Unexamined Patent Application Publication No. 2004-179255). Thereby, as shown in FIG. 34, a parasitic capacity C102 is formed at an interface between the deep n-type well layer 143 and the n-type well layer 144 on a side closer to the analog circuit 110, and a parasitic capacity C103 is formed at an interface between the deep n-type well layer 143 and the n-type well layer 144 on a side opposite to the side closer to the analog circuit 110, and the analog circuit 110 is electrically connected to the p-type semiconductor substrate 140 through the parasitic capacities C101, C102 and C103 which are connected in series, so, compared to the case where the deep n-type well layer 143 and the n-type well layer 144 are not arranged, the impedance in a low-frequency region between the analog circuit 110 and the p-type semiconductor substrate 140 can be increased. In a high-frequency, the impedance can be relatively high. As a result, the analog circuit 110 can be less susceptible to the potential of the p-type semiconductor substrate 140.